1. Field of the Invention
This invention relates to different amplifier circuits, and more particularly to differential amplifier circuits employing junction field effect transistors (JFETs) as the differential sensing elements.
2. Description of the Related Art
It is generally desirable to reduce input bias currents in numerous types of electrical circuits. In differential amplifiers which employ JFETs as the differential elements, input bias currents may be attributed to four principal factors:
(1) Impact ionization currents resulting from avalanche multiplication;
(2) Generation currents formed within the space charge region due to generation-recombination centers;
(3) Epitaxial-to-substrate junction leakage currents, for circuits in which junction isolation rather than dielectric isolation is used; and
(4) Diffusion currents resulting from electron-hole pairs generated outside of the space charge region diffusing into the space charge region.
Efforts to reduce the input bias current have previously focused on reducing the epitaxial-substrate junction leakage current by the introduction of various compensating currents. These efforts have not addressed the effect of impact ionization current, which can be quite significant once JFETs are operated at high currents and with large gate-drain voltages.
It is normally desirable to operate the JFETs in the saturated region, where they exhibit a high output impedance. Saturation is reached when the gate-drain voltage exceeds the device's pinchoff voltage (V.sub.p) In this mode a region of the JFET channel is pinched off, and the drain current that continues to flow is substantially independent of variations in the gate-drain voltage. To assure that the JFETs remain saturated their gate-drain voltages may be held at a level much greater than V.sub.p, but this substantially increases the impact ionization current contribution to input bias current.
A different approach to reducing the input bias current of a JFET differential amplifier stage, in which the gate-drain voltages of the JFETs are set at a level at which the effect of impact ionization current on the total input bias current is quite small, is disclosed in U.S. Pat. No. 4,538,115, issued Aug. 27, 1985 to the present inventor and assigned to Precision Monolithics, Inc. In this patent, a pair of input JFETs are connected in a differential stage and supplied with sufficient current to establish their gate-source voltages at less than V.sub.p. A second pair of JFETs are cascoded with the input pair, with their gates held at substantially the same voltage as the source voltages of the input pair. The JFETs are each supplied with a current approximately equal to 0.25 I.sub.DSS (defined as the drain current that will flow when the gate and source of a JFET are tied together), thereby utilizing a known JFET relationship to establish a gate-source voltage for each of the input and cascoded JFETs approximately equal to 0.5 V.sub.p. The cumulative gate-source voltages of the input and cascoded JFETs produce gate-drain voltages for the input pair approximately equal to V.sub.p, the minimum voltage necessary to keep the input JFETs saturated.
In the preferred embodiment, an additional pair of JFETs are added to buffer the input JFETs from large capacitances that can develop at the gates of the cascoded JFETs. The gate and source of one of the additional JFETs are connected together to a positive voltage bus, forcing it to carry a current equal to I.sub.DSS. This current is delivered to the source-drain circuit of the other additional JFET, which accordingly also exhibits a substantially zero source-gate voltage. While the source-gate voltage of the latter JFET is connected in series between the sources of the input JFETs and the gates of the cascoded JFETs, deliberately holding its source-gate voltage at a substantially zero level assured that the buffered transistors would not interfere with the circuit's AC operation.
While the approach taken in this patent is effective in reducing the circuit's input bias current, the cascoded JFETs have to be relatively large for their gate-source voltages to properly bias the input JFETs. This reduces the area available on the chip for other circuitry. In addition, the input JFETs themselves are relatively large.